The present invention relates to a semiconductor circuit. More particularly, it relates to a circuit arrangement which is well suited for operating an emitter-coupled logic (ECL) circuit or a differential amplifier circuit with low power consumption and at high speed.
Heretofore, a circuit arrangement as shown by way of example in FIG. 1 has been extensively employed for an emitter-coupled logic (ECL) circuit which has an emitter-follower output.
Referring to FIG. 1, symbols IN1 and IN2 denote input terminals, symbol I.sub.1 the current of a constant-current source, symbol V.sub.EE a minus supply voltage, symbol R.sub.1 a load resistance, symbol R.sub.T a terminating resistance, symbol V.sub.T a minus supply voltage for termination, symbol OUT an output terminal, and symbols Q.sub.1, Q.sub.2 and Q.sub.3 N-P-N bipolar transistors.
In the circuit of FIG. 1, letting V.sub.OH indicate the output potential of the output terminal OUT in the case where the transistor Q.sub.1 is conductive with the transistor Q.sub.2 being nonconductive, and letting V.sub.OL indicate the output potential of the output terminal OUT in the reverse case where the transistor Q.sub.2 is conductive with the transistor Q.sub.1 being nonconductive, the values of the potentials V.sub.OH and V.sub.OL are respectively expressed by the following equations (1) and (2): EQU V.sub.OH =-I.sub.BH R.sub.1 -V.sub.BE ( 1) EQU V.sub.OL =-I.sub.1 R.sub.1 -I.sub.BL R.sub.1 -V.sub.BE ( 2)
Here, I.sub.BH denotes a current which flows through the base of the transistor Q.sub.3 when the transistor Q.sub.2 is nonconductive, V.sub.BE the base-emitter forward voltage of the transistor Q.sub.3, and I.sub.BL a current which flows through the base of the transistor Q.sub.3 when the transistor Q.sub.2 is conductive.
The above equation (1) gives a value obtained by subtracting the product between I.sub.BH and R.sub.1 (namely, the component of a voltage drop across the collector resistance R.sub.1) and the component of a voltage drop across the base and emitter of the transistor Q.sub.3 from an earth potential, and this value is the output potential delivered when the transistor Q.sub.2 is nonconductive. On the other hand, the above equation (2) gives a value obtained in such a way that the product between the current I.sub.1 passing through the transistor Q.sub.2 and the resistance R.sub.1, the product between the current flowing across the base and emitter of the transistor Q.sub.3 via the resistance R.sub.1 and this resistance R.sub.1, and the component of the voltage drop across the base and emitter of the transistor Q.sub.3 are subtracted from the earth potential, and this value is the output potential delivered when the transistor Q.sub.2 is conductive.
Meanwhile, the high output potential V.sub.OH usually represents logic `1` and has a value of -0.8--0.9 V. The low output potential V.sub.OL usually represents logic `0` and has a value of -1.6--1.7 V. An output amplitude (V.sub.OH -V.sub.OL) is roughly equal to the product between I.sub.1 and R.sub.1, and is ordinarily required to be, at least, 0.8 V.
Next, FIG. 2 is a diagram in the case where a plurality of such prior-art ECL circuits are connected in parallel.
The wired-OR connection has been extensively employed as a circuit wherein, as shown in FIG. 2, the plurality of ECL circuits are coupled between chips or within an identical chip so as to execute logic processing. This connection is such that a plurality of emitter outputs are connected to one another and then terminated at the terminating voltage V.sub.T by the terminating resistance R.sub.T.
By the way, in the circuit of FIG. 2, symbols Q.sub.1 -Q.sub.9 denote N-P-N bipolar transistors, symbols I.sub.1 -I.sub.n the currents of constant-current sources, symbols IN11-IN1n and IN21-IN2n input terminals, and symbols R.sub.11 -R.sub.1n collector load resistances. The other symbols are the same as in FIG. 1.
Such a prior-art circuit has been so arranged that the outputs of a large number of nonselected circuits are brought to the low potential, and that the information `1` or `0` of one selected circuit is obtained at the output terminal OUT. It has accordingly been necessary that the corresponding ones of the currents I.sub.1 -I.sub.n are kept flowing also through the large number of nonselected circuits at all times, and that the corresponding ones of the inputs IN21-IN2n are held at a high potential. The reason is that, assuming the currents of the nonselected circuits to be zero, the emitter outputs of the nonselected circuits become the high potential irrespective of the potentials of the inputs IN21-IN2n, so the information `1` or `0` from the selected circuit is neglected. Accordingly, the currents I.sub.1 -I.sub.n of all the circuits need to be kept flowing.
In order to reduce the power consumption of the ECL circuit in FIG. 1, various methods have been considered. Now, when the value of the current I.sub.1 of the constant-current source is made small with the intention of lowering the power, the value of the resistance R.sub.1 needs to be set large for the purpose of attaining the prescribed output amplitude. By way of example, for the purpose of attaining an output amplitude equal to one in the case where the current I.sub.1 is 4 mA and where the resistance R.sub.1 is 250.OMEGA., the resistance R.sub.1 needs to be set at 500.OMEGA. when the current I.sub.1 is halved to 2 mA, and the resistance R.sub.1 needs to be set at 1 k.OMEGA. when the current I.sub.1 is reduced to 1 mA.
Meanwhile, as apparent from the preceding equation (1), the high output potential V.sub.OH is affected by the product between the resistance R.sub.1 and the base current I.sub.BH of the emitter-follower transistor Q.sub.3. Letting I.sub.OH denote the output current of the emitter follower Q.sub.3 generated when the output is the high potential V.sub.OH, this output current I.sub.OH becomes about 24 mA for the output terminating conditions of R.sub.T =50.OMEGA. and V.sub.T =-2 V. Incidentally, the term I.sub.BH .times.R.sub.1 in the preceding equation (1) can be replaced with the following equation: EQU I.sub.BH .times.R.sub.1 =(I.sub.OH /h.sub.FE).times.R.sub.1 ( 3)
where h.sub.FE indicates the current gain of the bipolar transistor Q.sub.3. On this occasion, in a case where the current gain h.sub.FE decreases due to enhancement in the withstand voltage of the bipolar transistor or where the resistance R.sub.1 increases due to the lowering of the power as stated above, the output voltage V.sub.OH lowers to -1 V or less in accordance with the above equation (3) and the preceding equation (1), to incur the problem that the output level specification of the ECL circuit fails to be satisfied.
Next, as illustrated in FIG. 2, for the purpose of taking the wired-OR logic by means of the prior-art ECL circuits, the constant currents I.sub.1 -I.sub.n need to be normally kept flowing in both the selected mode and the nonselected mode. This incurs the problem that the power consumption increases.
Meanwhile, as a prior-art logic circuit of small amplitude and high speed, there has been a current switching circuit (also called "CML (current-mode logic) circuit") wherein the emitter currents of, for example, the ECL circuit as stated above are switched to change the collector voltages thereof. In this circuit, each bipolar transistor is operated in its unsaturated region in order to avoid the lowering of an operating speed which is the disadvantage of a saturation type switching circuit. Although the circuit exhibits the high operating speed, it has the problem that the power consumption is still high because the constant current is normally kept flowing therethrough. For the purpose of lowering the power consumption, therefore, a circuit system for changing-over consumptive currents between in an operating period and in a standby period has been proposed in, for example, the official gazette of Japanese Patent Application Publication No. 3219/1978.
As shown in FIG. 3, the prior-art technique of the logic circuit is such that, in the constant-current source of the ECL circuit configured of a bipolar transistor Q.sub.303 and a resistance R.sub.303, a pulsed control voltage .0..sub.OP is impressed on the base of the transistor Q.sub.303, thereby to turn "on" and "off" the current source. Since the current is thus caused to flow during only the operating period, the power consumption is somewhat lowered.
This circuit, however, has the problem that, when the current of the current source is cut off or decreased, the output becomes a high potential or the output amplitude changes.
FIG. 4 is a diagram showing the prior-art circuit disclosed in the aforementioned official gazette. In this circuit, a current control signal .0. is used for controlling transistors Q.sub.105, Q.sub.106 and Q.sub.107 which constitute the current sources of the transistors Q.sub.101 and Q.sub.102 of a current switching circuit and the transistors Q.sub.103 and Q.sub.104 of emitter-follower circuits Symbols IN.sub.401 and IN.sub.402 denote input terminals, and symbols O.sub.401 and O.sub.402 output terminals. When the potential of the current control signal .0. is a high level, the three current sources formed of the bipolar transistors Q.sub.105, Q.sub.106 and Q.sub.107 and resistances R.sub.103, R.sub.104 and R.sub.105 cause predetermined currents to flow, whereas when the potential of the current control signal .0. is a low level, the three current sources are turned "off." Thus, this circuit consumes the currents during only the operating period (namely, while the signal .0. is at the high level) and can render the current consumption null during the standby period (namely, while the signal .0. is at the low level), so that the power consumption can be reduced. Such a current control method is effective for lowering the power of a memory LSI or logic LSI. Here, the current control signal .0. is a direct input signal which is applied from outside or a signal which is generated by an internal circuit with the external input signal.
In the prior art output stated above, quite no consideration is given to the output potentials and internal potentials during the standby period, namely, during the turn-off of the transistors Q.sub.105, Q.sub.106 and Q.sub.107. On such an occasion, the saturation of bipolar transistors at the succeeding stages or the lowering of the operating speed of the circuit itself might be incurred for reasons to be elucidated below:
In general, the base-emitter voltage V.sub.BE of a bipolar transistor is expressed by the following equation: ##EQU1##
Here, I.sub.E denotes the emitter current of the bipolar transistor, I.sub.S the reverse saturation current thereof, k Boltzmann's constant, T an absolute temperature, and q the electron charge. The value of the voltage V.sub.BE is about 0.8 V in the state in which the current of ordinary magnitude flows. However, when the current I.sub.E becomes 1/10, the V.sub.BE value decreases in an amount of about 60 mV in accordance with the above equation. Accordingly, when the emitter currents of the transistor Q.sub.103 and Q.sub.104 become zero in the standby period, the potentials of the outputs O.sub.401 and O.sub.402 come closer to a supply voltage V.sub.CC.
In actuality, the emitter currents do not become perfectly zero, but minute junction leakage currents flow through the transistors Q.sub.103 and Q.sub.104. Therefore, the potentials of the outputs O.sub.401 and O.sub.402 become values lower than the supply voltage V.sub.CC, but they become approximately 0.5 V higher than the normal high potential (V.sub.CC -0.8 V) in the operating period.
In addition, since the potentials depend upon the leakage currents, they disperse greatly.
When the potentials of the outputs O.sub.401 and O.sub.402 heighten in this manner, the bipolar transistors at the succeeding stages become liable to saturation, and moreover, the design of the circuit becomes difficult due to the great dispersions.
Besides, the potential of the common emitter point of the transistors Q.sub.101 and Q.sub.102 approaches the high potential of the input IN.sub.401 or IN.sub.402 for the same reason as in the foregoing when no current is caused to flow. This leads to the problem that the potential fluctuation of the common emitter point at the shift from the standby period to the operating period enlarges to delay the current switching operations of the transistor Q.sub.101 and Q.sub.102.